Not applicable.
Not applicable.
1. Field of the Invention
The present invention generally relates to a memory cell. More particularly, the invention relates to a volatile memory cell reconfigured as a non-volatile memory cell. More particularly still, the invention relates to a volatile static random access memory (xe2x80x9cSRAMxe2x80x9d) memory cell that has been configured to operate as non-volatile, read only memory cell.
2. Background of the Invention
Virtually all electronic equipment from calculators to computers to DVD players to electronics in an automobile include some type of memory storage. Storage can take the form of a drive such as a floppy drive, hard drive or CD ROM. Alternatively, storage may be implemented in the form of a solid state memory device. The present disclosure pertains to this latter class of storage technology.
Solid state memory itself can be implemented in a variety of forms. For purposes of understanding the memory improvements disclosed herein, solid state memory generally can be viewed in two formsxe2x80x94volatile and non-volatile. Volatile memory can store information as long as power is supplied to the device. Once power is removed from the device, the information stored therein is lost. Examples of volatile memory include static random access memory (xe2x80x9cSRAMxe2x80x9d) and a dynamic RAM (xe2x80x9cDRAMxe2x80x9d), which are well known to those of ordinary skill in the art. By contrast, non-volatile memory retains its contents even when power is removed from the device. An example of a non-volatile memory device is a read only memory (xe2x80x9cROMxe2x80x9d) device, which also is well known to those of ordinary skill in the art.
A microprocessor is a semiconductor device that retrieves and executes instructions. The instructions may be referred to as xe2x80x9csoftwarexe2x80x9d when the instructions are stored on a drive or xe2x80x9cfirmwarexe2x80x9d when the instructions are stored on a non-volatile memory device such as a ROM. In some situations, software and firmware are executed directly from their permanent storage location (i.e., drive, ROM). In other situations, this is not the case. Instead, software or firmware instruction are retrieved from their permanent storage location, copied to volatile RAM memory coupled to the processor device and executed therefrom. Thus, when it is desired to execute a particular application, the instructions comprising that application first are copied from their permanent storage location (e.g., a hard disk drive or ROM) to non-volatile memory (e.g., SRAM or DRAM). Then, the instructions are retrieved from the non-volatile memory into the microprocessor for processing and execution.
An exemplary application of this process is a digital signal processor (xe2x80x9cDSPxe2x80x9d) that does not include ROM memory on the DSP chip itself. Such a device will have on-chip RAM, such as SRAM, for temporarily storing data and for storing instructions pending execution by the CPU core. The instructions are retrieved from an external ROM device over a bus interconnecting the ROM device to the DSP.
This configuration, namely, external ROM having firmware that is copied over a bus to a DSP device, generally works well. For various reasons, however, it is often desirable to have ROM memory implemented inside the DSP chip. For example, security of sensitive information contained in the firmware can be better protected if the firmware is stored permanently in ROM inside the DSP. Further, it is faster to copy firmware from ROM internal to the DSP to RAM internal to the DSP than from external ROM to RAM internal to the DSP. Thus, while in many systems firmware is permanently stored in ROM external to the DSP, it often is desirable for the firmware to be permanently stored in ROM internal to the DSP.
Of course, a DSP, that does not have on-chip ROM, can be redesigned to include such ROM in its design. Such a design effort, however, requires considerable time and money and thus the xe2x80x9ctime-to-marketxe2x80x9d for such a device may be significantly long. Accordingly, a solution to this problem is needed whereby a device (e.g., a DSP) can be implemented with non-volatile memory in a way that minimizes the time to market.
The problems noted above are solved in large part by modifying a conventional volatile SRAM cell into a non-volatile, read only memory cell. This permits a device (e.g., a microprocessor or digital signal processor) whose design currently includes on-chip SRAM, but no ROM, to have non-volatile, read only memory with minimal redesign and development effort. The modifications made to the already present SRAM are fairly minimal resulting in much of the modified SRAM being largely unchanged. Because existing on chip, volatile memory is used largely as is with fairly minimal modifications to make the memory non-volatile, the time-to-market for such a device is much shorter than it would have been had the device been redesigned to include conventional ROM.
In accordance with one embodiment of the invention, a memory cell in which a bit can be stored comprises: a first transistor having a gate, a source and a drain; a second transistor having a gate, a source and a drain; a third transistor having a gate, a source and a drain; and a fourth transistor having a gate, a source and a drain, wherein the first, second, third and fourth transistors are coupled together. Further, the gates of the first and second transistors are connected together and to a power supply voltage and the gates of the third and fourth transistors are connected together and to a low signal.
In accordance with another embodiment, a memory cell in which a bit can be stored comprises: a first transistor having a gate, a source and a drain; a second transistor having a gate, a source and a drain; a third transistor having a gate, a source and a drain; and a fourth transistor having a gate, a source and a drain, wherein the first, second, third and fourth transistors are coupled together. Further, the gates of the first and second transistors are connected together and to a power supply voltage and the gates of the third and fourth transistors are connected together at a connection node and a means is included for providing a low signal level on the connection node. The power supply voltage in this embodiment can be a positive Vdd voltage or ground.